MPC8540 datasheet(456/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-2

Freescale Semiconductor

I2C Interface

11.1.1 Overview

The two-wire I

2C bus minimizes interconnections between devices. The synchronous,

multiple-master I2C bus allows the connection of additional devices to the bus for expansion and

system development. The bus includes collision detection and arbitration that prevent data

corruption if two or more masters attempt to control the bus simultaneously.

11.1.2

Features

The I

2C interface includes the following features:

•

Two-wire interface

•

Multiple-master operation

•

Arbitration lost interrupt with automatic mode switching from master to slave

•

Calling address identification interrupt

•

START and STOP signal generation/detection

•

Acknowledge bit generation/detection

•

Bus busy detection

•

Software-programmable clock frequency

•

Software-selectable acknowledge bit

•

On-chip filtering for spikes on the bus

11.1.3

Modes of Operation

The I

2C unit on this device can operate in one of the following modes:

•

Master mode—The I

2C is the driver of the SDA line. It cannot use its own slave address as

a calling address. The I

2C cannot be a master and a slave simultaneously.

•

Slave mode—The I

2C is not the driver of the SDA line. The module must be enabled before

a START condition from a non-I2C master is detected.

•

Interrupt-driven byte-to-byte data transfer—When successful slave addressing is achieved

(and SCL returns to zero), the data transfer can proceed on a byte-to-byte basis in the

direction specified by the R/W bit sent by the calling master. Each byte of data must be

followed by an acknowledge bit, which is signalled from the receiving device. Several

bytes can be transferred during a data transfer session.

•

Boot sequencer mode—This mode can be used to initialize the configuration registers in

the device after the I

2C module is initialized. Note that the MPC8540 powers up with boot

sequencer mode disabled as a default, but this mode can be selected with the

cfg_boot_seq[0:1] power-on reset (POR) configuration signals that are located on the

LGPL3 and LGPL5 signals.

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