MPC8540 datasheet(457/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-3

Additionally, the following three I

2C-specific states are defined for the I2C interface:

•

START condition—This condition denotes the beginning of a new data transfer (each data

transfer contains several bytes of data) and awakens all slaves.

•

Repeated START condition—A START condition that is generated without a STOP

condition to terminate the previous transfer.

•

STOP condition—The master can terminate the transfer by generating a STOP condition to

free the bus.

11.2 External Signal Descriptions

The following sections give an overview of signals and provide detailed signal descriptions.

11.2.1

Signal Overview

The I2C interface uses the SDA and SCL signals, described in Table 11-1, for data transfer. All

devices connected to these two signals must have open-drain or open-collector outputs. A logical

AND function is performed on both signals with external pull-up resistors. Note that the signal

patterns driven on SDA represent address, data, or read/write information at different stages of the

protocol.

11.2.2

Detailed Signal Descriptions

SDA and SCL, described in Table 11-2, serve as a communication interconnect with other devices.

All devices connected to these two signals must have open-drain or open-collector outputs. The

logic AND function is performed on both of these signals with external pull-up resistors. Refer to

the MPC8540 Integrated Host Processor Hardware Specifications for the electrical characteristics

of these signals.

Table 11-1. I2C Interface Signal Description

Signal Name Idle State I/O

State Meaning

Serial Clock

(SCL)

HIGH

When the I2C module is idle or acts as a slave, SCL defaults as an input. The unit uses

SCL to synchronize incoming data on SDA. The bus is assumed to be busy when SCL

is detected low.

As a master, the I2C module drives SCL along with SDA when transmitting. As a slave,

the I2C module drives SCL low for data pacing.

Serial Data

(SDA)

HIGH

When the I2C module is idle or in a receiving mode, SDA defaults as an input. The unit

receives data from other

I2C devices on SDA. The bus is assumed to be busy when

SDA is detected low.

When writing as a master or slave, the I2C module drives data on SDA synchronous

to SCL.

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