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MPC8540 Datasheet(PDF) 459 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 459 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
11-5
11.3.1.1
I2C Address Register (I2CADR)
Figure 11-2 shows the I2CADR register, which contains the address to which the I
2C interface
responds when addressed as a slave. Note that this is not the address that is sent on the bus during
the address-calling cycle when the I
2C module is in master mode.
Figure 11-2. I2C Address Register (I2CADR)
Table 11-4 describes the bit settings of I2CADR.
11.3.1.2
I2C Frequency Divider Register (I2CFDR)
Figure 11-3 shows the bits of the I
2C frequency divider register.
Figure 11-3. I2C Frequency Divider Register (I2CFDR)
0
67
R
ADDR
W
Reset
0000_0000
Offset
0x0_3000
Table 11-4. I2CADR Field Descriptions
Bits Name
Description
0–6 ADDR Slave address. Contains the specific slave address that is used by the I2C interface. Note that the default
mode of the I2C interface is slave mode for an address match. Note that an address match is one of the
conditions that can cause I2CSR[MIF] to be set, signaling an interrupt pending condition.
7—
Reserved
012
7
R
FDR
W
Reset
0000_0000
Offset
0x0_3004



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