MPC8540 datasheet(462/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-8

Freescale Semiconductor

I2C Interface

Figure 11-5. I2C Status Register (I2CSR)

Table 11-7 describes the bit settings of the I2CSR.

123

456

MCF

MAAS

MBB

MAL

BCSTM

SRW

MIF

RXAK

Reset

1000_0001

Offset

0x0_300C

Table 11-7. I2CSR Field Descriptions

Bits

Name

Description

MCF

Data transfer. When one byte of data is transferred, the bit is cleared. It is set by the falling edge of the

9th clock of a byte transfer.

0 Byte transfer in progress. MCF is cleared under the following conditions:

•When I2CSR is read in receive mode or

•When I2CDR is written in transmit mode

1 Byte transfer is completed

MAAS

Addressed as a slave. When the value in I2CDR matches with the calling address, this bit is set. The

processor is interrupted, if I2CCR[MIEN] is set. Next, the processor must check the SRW bit and set

I2CCR[MTX] accordingly. Writing to the I2CCR automatically clears this bit.

0 Not addressed as a slave

1 Addressed as a slave

MBB

Bus busy. Indicates the status of the bus. When a START condition is detected, MBB is set. If a STOP

condition is detected, it is cleared.

0I2C bus is idle

1I2C bus is busy

MAL

Arbitration lost. Automatically set when the arbitration procedure is lost. Note that the device does not

automatically retry a failed transfer attempt.

0 Arbitration is not lost. Can only be cleared by software

1 Arbitration is lost

BCSTM Broadcast match

0 There has not been a broadcast match.

1 The calling address matches with the broadcast address instead of the programmed slave address.

This will also be set if this I2C drives an address of all 0s and broadcast mode is enabled.

SRW

Slave read/write. When MAAS is set, SRW indicates the value of the R/W command bit of the calling

address, which is sent from the master.

0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave. This bit is valid only when both of the following conditions

are true:

•A complete transfer occurred and no other transfers have been initiated.

•The I2C interface is configured as a slave and has an address match.

By checking this bit, the processor can select slave transmit/receive mode according to the command

of the master.

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