MPC8540 datasheet(466/1302 Pages) FREESCALE

466 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-12

Freescale Semiconductor

I2C Interface

The I

2C module responds to a general call (broadcast) command when I2CCR[BCST] is set. A

broadcast address is always zero; however the I

2C module will not check the R/W bit. The second

byte of the broadcast message is the master address. Because the second byte is automatically

acknowledged by hardware, the receiver device software must verify that the broadcast message

is intended for itself by reading the second byte of the message. If the master address is for another

receiver device and the third byte is a write command, software can ignore the third byte during

the broadcast. If the master address is for another receiver device and the third byte is a read

command, software must write 0xFF to I2CDR with I2CCR[TXAK] = 1, so that it does not

interfere with the data written from the addressed device.

Each data byte is 8 bits long. Data bits can be changed only while SCL is low and must be held

stable while SCL is high, as shown in Figure 11-8. There is one clock pulse on SCL for each data

bit, and the most significant bit (msb) is transmitted first. Each byte of data must be followed by

an acknowledge bit, which is signaled from the receiving device by pulling the SDA line low at

the 9th clock. Therefore, one complete data byte transfer takes 9 clock pulses. Several bytes can

be transferred during a data transfer session.

If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave.

The master can then generate a stop condition to abort the data transfer or a START condition

(repeated START) to begin a new calling.

If the master receiver does not acknowledge the slave transmitter after a byte of transmission, the

slave interprets that the end-of-data has been reached. Then the slave releases the SDA line for the

master to generate a STOP or a START condition.

11.4.1.3

Repeated START Condition

Figure 11-8 shows a repeated START condition, which is generated without a STOP condition that

can terminate the previous transfer. The master uses this method to communicate with another

slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.

11.4.1.4

STOP Condition

The master can terminate the transfer by generating a STOP condition to free the bus. A STOP

condition is defined as a low-to-high transition of the SDA signal while SCL is high. For more

information, see Figure 11-8. Note that a master can generate a STOP even if the slave has

transmitted an acknowledge bit, at which point the slave must release the bus. The STOP condition

is initiated by a software write that clears I2CCR[MSTA].

As described in Section 11.4.1.3, “Repeated START Condition,” the master can generate a START

condition followed by a calling address without generating a STOP condition for the previous

transfer. This is called a repeated START condition.

MPC8540 Datasheet(PDF) 466 Page - Freescale Semiconductor, Inc

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