MPC8540 datasheet(469/1302 Pages) FREESCALE

469 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-15

If the I

2C module is enabled in the middle of an ongoing byte transfer, the interface behaves as

follows:

•

Slave mode—The I

2C module ignores the current transfer on the bus and starts operating

whenever a subsequent START condition is detected.

•

Master mode—The I

2C module cannot tell whether the bus is busy; therefore, if a START

condition is initiated, the current bus cycle can be corrupted. This ultimately results in the

current bus master of the I

2C interface losing arbitration, after which bus operations return

to normal.

11.4.2.1

Arbitration Control

The arbitration control block controls the arbitration procedure of the master mode. A loss of

arbitration occurs whenever the master detects a 0 on the external SDA line while attempting to

drive a 1, tries to generate a START or restart at an inappropriate time, or detects an unexpected

STOP request on the line.

In master mode, arbitration by the master is lost (and I2CSR[MAL] is set) under the following

conditions:

•

SDA samples low when the master drives high during an address or data-transmit cycle

(transmit).

•

SDA samples low when the master drives high during a data-receive cycle of the

acknowledge (Ack) bit (receive).

•

A START condition is attempted when the bus is busy.

•

A repeated START condition is requested in slave mode.

•

A start condition is attempted when the requesting device is not the bus owner

•

Unexpected STOP condition detected

Note that the I2C module does not automatically retry a failed transfer attempt.

11.4.3

Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can

hold SCL low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and

forces the master clock into wait states until the slave releases the SCL line.

11.4.4

Clock Control

The clock control block handles requests from the clock signal for transferring and controlling data

for multiple tasks.

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