MPC8540 datasheet(471/1302 Pages) FREESCALE

471 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-17

The sampling rate is equal to a binary value stored in the frequency register I2CDFSRR. The

duration of the sampling cycle is controlled by a down counter. This allows a software write to the

frequency register to control the filtered sampling rate.

11.4.4.3

Clock Stretching

Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the

master has driven the SCL line low, the slave can drive SCL low for the required period and then

release it. If the slave SCL low period is greater than the master SCL low period, then the resulting

SCL bus signal low period is stretched.

11.4.5

Boot Sequencer Mode

If boot sequencer mode is selected on POR (by the settings on the LGPL3 and LGPL5 reset

configuration signals, as described in Section 4.4.3.6, “Boot Sequencer Configuration”), the I2C

module communicates with one or more EEPROMs through the I

2C interface. The EEPROM(s)

can be programmed to initialize one or more configuration registers of this integrated device.

The boot sequencer mode also supports an extension of the standard I

2C interface that uses more

address bits to allow for EEPROM devices that have more than 256 bytes, and this extended

addressing mode is selectable during POR with a different encoding on the LGPL3 and LGPL5

reset configuration signals (see Section 4.4.3.6, “Boot Sequencer Configuration”). In this mode,

only one EEPROM device may be used, and the maximum number of registers is limited by the

size of the EEPROM.

If the standard I2C interface is used, the I2C module addresses the first EEPROM, and reads

256 bytes. Then it issues a repeated start and addresses the next EEPROM address. This sequence

continues until the CONT bit is cleared. If the last register is not detected before wrapping back to

the first address, an error condition is detected. In other words, if the CONT bit for not cleared on

the final 7 bytes, an error condition is detected, causing the device to hang and the HRESET_REQ

signal to assert externally. The I

2C module continues to read from the EEPROM as long as the

continue (CONT) bit is set in the EEPROM. The CONT bit resides in the address/attributes field

that is transferred from the EEPROM, as described in Section 11.4.5.1, “EEPROM Calling

Address.” There should be no other I2C traffic when the boot sequencer is active.

Note that as described in Section 4.4.3.6, “Boot Sequencer Configuration,” the default value for

the LGPL3 and LGPL5 reset configuration pins is 0b11, which corresponds to the I

2C boot

sequencer being disabled at power-up.

11.4.5.1

EEPROM Calling Address

The MPC8540 uses 0b101_0000 for the EEPROM calling address. The first EEPROM to be

addressed must be programmed to respond to this address, or an error is generated. If more

EEPROMs are used, they are addressed in sequential order.

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