MPC8540 datasheet(474/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-20

Freescale Semiconductor

I2C Interface

11.5 Initialization/Application Information

This section describes some programming guidelines recommended for the I

2C interface.

Figure 11-11 is a recommended flowchart for I2C interrupt service routines.

The I

2C registers in this chapter are shown in big-endian format. If the system is in little-endian

mode, software must swap the bytes appropriately. This appropriate byte swapping is needed as

2C registers are byte registers. Also, an msync assembly instruction must be executed after each

2C register read/write access to guarantee in-order execution.

The I2C controller does not guarantee its recovery from all illegal I2C bus activity. In addition, a

malfunctioning device may hold the bus captive. A good programming practice is for software to

rely on a watchdog timer to help recover from I2C bus hangs. The recovery routine should also

handle the case when the status bits returned after an interrupt are not consistent with what was

expected due to illegal I2C bus protocol behavior.

11.5.1

Initialization Sequence

A hard reset initializes all the I2C registers to their default states. The following initialization

sequence initializes the I

2C unit:

1. All I

2C registers must be located in a cache-inhibited page.

2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency

from the CCB (platform) clock.

ACS

BYTE_EN

ADDR[0–1]

Last Configuration

Preload Command

ADDR[2–9]

ADDR[10–17]

DATA[0–7]

DATA[8–15]

DATA[16–23]

DATA[24–31]

End Command

CRC[0–7]

Cyclic Redundancy

Check

CRC[8–15]

CRC[16–23]

CRC[24–31]

Figure 11-10. EEPROM Contents (continued)

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