MPC8540 datasheet(475/1302 Pages) FREESCALE

475 / 1302 page

Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-21

3. Update I2CADR to define the slave address for this device.

4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interrupt-enable

or disable.

5. Set the I2CCR[MEN] to enable the I

2C interface.

11.5.2 Generation of START

After initialization, the following sequence can be used to generate START:

1. If the device is connected to a multimaster I

2C system, test the state of I2CSR[MBB] to

check whether the serial bus is free (I2CSR[MBB] = 0) before switching to master mode.

2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode

(set I2CCR[MTX]) for the address cycle.

3. Write the slave address being called into I2CDR. The data written to I2CDR[0–6]

comprises the slave calling address. I2CCR[MTX] indicates the direction of transfer

(transmit/receive) required from the slave.

The scenario above assumes that the I2C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any

time, an I

2C interrupt is generated (provided interrupt reporting is enabled with

I2CCR[MIEN] =1) so that the I2C interrupt handler can handle the interrupt.

11.5.3

Post-Transfer Software Response

Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]),

which indicates that one byte has been transferred. The I

2C interrupt bit (I2CSR[MIF]) is also set

and an interrupt is generated to the processor if the interrupt function is enabled during the

initialization sequence (I2CCR[MIEN] is set). In the interrupt handler, software must take the

following steps:

1. Clear I2CSR[MIF]

2. Read the contents of the I

2C data register (I2CDR) in receive mode or write to I2CDR in

transmit mode. Note that this causes I2CSR[MCF] to be cleared. See Section 11.5.8,

“Interrupt Service Routine Flowchart.”

When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If

master receive mode is required, I2CCR[MTX] must be toggled at this stage. See Section 11.5.8,

“Interrupt Service Routine Flowchart.”

If the interrupt function is disabled, software can service the I2CDR in the main program by

monitoring I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF]

because MCF behaves differently when arbitration is lost. Note that interrupt or other bus

conditions may be detected before the I

2C signals have time to settle. Thus, when polling

MPC8540 Datasheet(PDF) 475 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 475 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL