MPC8540 datasheet(472/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-18

Freescale Semiconductor

I2C Interface

11.4.5.2

EEPROM Data Format

The I

2C module expects that a particular data format be used for data in the EEPROM. A preamble

should be the first 3 bytes programmed into the EEPROM. It should have a value of 0xAA55AA.

The I

2C module checks to ensure that this preamble is correctly detected before proceeding

further. Following the preamble, there should be a series of configuration registers (known as

programmed according to a particular format, as shown in Figure 11-9. The first 3 bytes hold the

attributes and address offset, as follows. The attributes contained are alternate configuration space

(ACS), byte enables, and continue (CONT). The boot sequencer expects the address offset to be a

32-bit (word) offset, that is, the 2 low-order bits are not included in the boot sequencer command.

For example, to access LAWBAR0 (byte offset of 0x00C08), the boot sequencer ADDR[0:17]

should be set to 0x00302.

After the first 3 bytes, 4 bytes of data should hold the desired value of the configuration register,

regardless of the size of the transaction. Byte enables should be asserted for any byte that will be

written to the configuration register, and they should be asserted contiguously, creating a 1-, 2-, or

4-byte write to a register. The boot sequencer assumes that a big-endian address is stored in the

EEPROM. In addition, byte enable bit 0 (bit 1 of the byte) corresponds to the most-significant byte

of data (data[0:7]), and byte enable bit 3 (bit 4 of the byte) corresponds to the LSB of data

(data[24:31]).

By setting ACS, an alternate configuration space address is prepended to the write request from

the boot sequencer. Otherwise, CCSRBAR is prepended to the EEPROM address.

If CONT is cleared, the first 3 bytes, including ACS, the byte enables, and the address, must also

be cleared. Also, the data contains the final cyclic redundancy check (CRC). A CRC-32 algorithm

is used to check the integrity of the data. The polynomial used is:

1 + x

1 + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32

CRC values are calculated using the above polynomial with a start value of 0xFFFF_FFFF and an

XOR with 0x0000_0000. The CRC should cover all bytes stored in the EEPROM prior to the

CRC. This includes the preamble, all register preloads, and the first 3 bytes of the last 7-byte

preload (which should be all zeros). If a preamble or CRC fail is detected, the device hangs and

the external HRESET_REQ signal asserts. If there is a preamble fail, the boot sequencer may

continue to pull I

2C pins low until a hard reset occurs.

MPC8540 Datasheet(PDF) 472 Page - Freescale Semiconductor, Inc