MPC8540 datasheet(468/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-14

Freescale Semiconductor

I2C Interface

The SCL signal corresponds to the internal SCL signal when one or more of the following

conditions are true in either master or slave mode:

•

Master mode

— Bus owner

— Lost arbitration

— START condition

— STOP condition

— Restart condition begin

— Restart condition end

•

Slave mode

— Address cycle

— Transmit cycle

— Ack cycle

11.4.1.6

Address Compare—Implementation Details

Address compare block determines if a slave has been properly addressed, either by its slave

address or by the general broadcast address (which addresses all slaves). The three performed

address comparisons are described as follows:

•

Whether a broadcast message has been received, to update the I2CSR

•

Whether the module has been addressed as a slave, to update the I2CSR and to generate an

interrupt

•

If the address transmitted by the current master matches the general broadcast address

11.4.2

Arbitration Procedure

The I

2C interface is a true multiple-master bus that allows more than one master device to be

connected on it. If two or more masters simultaneously try to control the bus, each master’s clock

synchronization procedure (including the I

2C module) determines the bus clock—the low period

is equal to the longest clock low period and the high is equal to the shortest one among the masters.

A bus master loses arbitration if it transmits a logic 1 on SDA while another master transmits a

logic 0. The losing masters immediately switch to slave-receive mode and stop driving the SDA

line. In this case, the transition from master to slave mode does not generate a STOP condition.

Meanwhile, the I

2C unit sets the I2CSR[MAL] status bit to indicate the loss of arbitration and, as

a slave, services the transaction if it is directed to itself.

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