MPC8540 datasheet(470/1302 Pages) FREESCALE

470 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-16

Freescale Semiconductor

I2C Interface

A 9-cycle data transfer clock is requested for the following conditions:

•

Master mode

— Transmit slave address after START condition

— Transmit slave address after restart condition

— Transmit data

— Receive data

•

Slave mode

— Transmit data

— Receive data

— Receive slave address after START or restart condition

11.4.4.1

Clock Synchronization

Due to the wire AND logic on the SCL line, a high-to-low transition on the SCL line affects all

devices connected on the bus. The devices begin counting their low period when the master drives

the SCL line low. After a device has driven SCL low, it holds the SCL line low until the clock high

state is reached. However, the change of low-to-high in a device clock may not change the state of

the SCL line if another device is still within its low period. Therefore, the synchronized clock

signal, SCL, is held low by the device with the longest low period. Devices with shorter low

periods enter a high wait state during this time. When all devices concerned have counted off their

low period, the synchronized SCL line is released and pulled high. Then there is no difference

between the devices’ clocks and the state of the SCL line, and all the devices begin counting their

high periods. The first device to complete its high period pulls the SCL line low again.

11.4.4.2

Input Synchronization and Digital Filter

The following sections describes the synchronizing of the input signals, and the filtering of the

SCL and SDA lines in detail.

11.4.4.2.1 Input Signal Synchronization

The input synchronization block synchronizes the input SCL and SDA signals to the system clock

and detects transitions of these signals.

11.4.4.2.2 Filtering of SCL and SDA Lines

The SCL and SDA inputs are filtered to eliminate noise. Three consecutive samples of the SCL

and SDA lines are compared to a pre-determined sampling rate. If they are all high, the output of

the filter is high. If they are all low, the output is low. If they are any combination of highs and

lows, the output is whatever the value of the line was in the previous clock cycle.

MPC8540 Datasheet(PDF) 470 Page - Freescale Semiconductor, Inc