MPC8540 datasheet(467/1302 Pages) FREESCALE

467 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-13

11.4.1.5

Protocol Implementation Details

The following sections give details of how aspects of the protocol are implemented in this I

module.

11.4.1.5.1 Transaction Monitoring—Implementation Details

The different conditions of the I2C data transfers are monitored as follows:

•

START conditions are detected when an SDA fall occurs while SCL is high.

•

STOP conditions are detected when an SDA rise occurs while SCL is high.

•

Data transfers in progress are canceled when a STOP condition is detected or if there is a slave

address mismatch. Cancellation of data transactions resets the clock module.

•

The bus is detected to be busy upon the detection of a START condition, and idle upon the

detection of a STOP condition.

11.4.1.5.2 Control Transfer—Implementation Details

The I2C module contains logic that controls the output to the serial data (SDA) and serial clock

(SCL) lines of the I

2C. The SCL output is pulled low as determined by the internal clock generated

in the clock module. The SDA output can only change at the midpoint of a low cycle of the SCL,

unless it is performing a START, STOP, or restart condition. Otherwise, the SDA output is held

constant.

The SDA signal is pulled low when one or more of the following conditions are true in either

master or slave mode:

•

Master mode

— Data bit (transmit)

— Ack bit (receive)

— START condition

— STOP condition

— Restart condition

•

Slave mode

— Acknowledging address match

— Data bit (transmit)

— Ack bit (receive)

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