MPC8540 datasheet(463/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-9

11.3.1.5

I2C Data Register (I2CDR)

The I2C data register is shown in Figure 11-6.

Figure 11-6. I2C Data Register (I2CDR)

Table 11-8 shows the bit descriptions for I2CDR.

MIF

Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request

(provided I2CCR[MIEN] is set).

0 No interrupt is pending. Can be cleared only by software.

1 Interrupt is pending. MIF is set when one of the following events occurs:

•One byte of data is transferred (set at the falling edge of the 9th clock).

•The value in I2CADR matches with the calling address in slave-receive mode.

•Arbitration is lost.

RXAK

Received acknowledge. The value of SDA during the reception of acknowledge bit of a bus cycle. If the

received acknowledge bit (RXAK) is low, it indicates that an acknowledge signal has been received

after the completion of eight bits of data transmission on the bus. If RXAK is high, it means no

acknowledge signal has been detected at the 9th clock.

0 Acknowledge received

1 No acknowledge received

DATA

Reset

0000_0000

Offset

0x0_3010

Table 11-8. I2CDR Field Description

Bits

Name

Description

0–7

DATA

Transmission starts when an address and the R/W bit are written to the data register and the I2C

interface performs as the master. A data transfer is initiated when data is written to the I2CDR. The

most significant bit is sent first in both cases. In the master receive mode, reading the data register

allows the read to occur, but also allows the I2C module to receive the next byte of data on the I2C

interface. In slave mode, the same function is available after it is addressed. Note that the very first

read is always a dummy read.

Table 11-7. I2CSR Field Descriptions (continued)

Bits

Name

Description

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