MPC8540 datasheet(461/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-7

Table 11-6 describes the bit settings of the I2CCR

11.3.1.4

I2C Status Register (I2CSR)

The status register, shown in Figure 11-5, is read only with the exception of the MIF and MAL

bits, which can be cleared by software. The MCF and RXAK bits are set at reset; all other I2CSR

bits are cleared on reset.

Table 11-6. I2CCR Field Descriptions

Bits Name

Description

MEN

Module enable. This bit controls the software reset of the I2C module.

0 The module is reset and disabled. When low, the interface is held in reset but the registers can still be

accessed.

1The I2C module is enabled. This bit must be set before any other control register bits have any effect.

All I2C registers for slave receive or master START can be initialized before setting this bit.

MIEN Module interrupt enable

0 Interrupts from the I2C module are disabled. This does not clear any pending interrupt conditions.

1 Interrupts from the I2C module are enabled. An interrupt occurs provided I2CSR[MIF] is also set.

MSTA Master/slave mode START

0 When this bit is changed from one to zero, a STOP condition is generated and the mode changes from

master to slave.

1 Cleared without generating a STOP condition when the master loses arbitration. When this bit is

changed from zero to one, a START condition is generated on the bus, and master mode is selected.

MTX

Transmit/receive mode select. This bit selects the direction of the master and slave transfers. When

configured as a slave, this bit should be set by software according to I2CSR[SRW]. In master mode, the

bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will

always be high. The MTX bit is cleared when the master loses arbitration.

0 Receive mode

1 Transmit mode

TXAK Transfer acknowledge. This bit specifies the value driven onto the SDA line during acknowledge cycles

for both master and slave receivers. The value of this bit only applies when the I2C module is configured

as a receiver, not a transmitter. It also does not apply to address cycles; when the device is addressed as

a slave, an acknowledge is always sent.

0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock bit after receiving one

byte of data.

1 No acknowledge signal response (high value on SDA) is sent.

RSTA Repeat START. Setting this bit always generates a repeated START condition on the bus, provides the

device with the current bus master. Attempting a repeated START at the wrong time (or if the bus is owned

by another master), results in loss of arbitration. Note that this bit is not readable, which means if a read

is performed to I2CCR[RSTA], a zero value will be returned.

No START condition is generated

1 Generates repeat START condition

6—

Reserved

BCST Broadcast

0 Disables the broadcast accept capability

1 Enables the I2C to accept broadcast messages at address zero

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