MPC8540 datasheet(458/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-4

Freescale Semiconductor

I2C Interface

11.3 Memory Map/Register Definition

Table 11-3 lists the I

2C–specific registers and their addresses.

11.3.1

This section describes the I

2C registers in detail.

NOTE

Reserved bits should always be written with the value they returned when

read. That is, the register should be programmed by reading the value,

modifying appropriate fields, and writing back the value. The return value

of the reserved fields should not be assumed, even though the reserved fields

return zero.

This note does not apply to the I2C data register (I2CDR).

Table 11-2. I2C Interface Signal—Detailed Signal Descriptions

Signal

I/O

Description

SCL

I/O

Serial clock. Performs as an input when the MPC8540 is programmed as an I2C slave. SCL also

performs as an output when the MPC8540 is programmed as an I2C master.

As outputs for the bidirectional serial clock, these signals operate as described below.

State

Meaning

Asserted/Negated—Driven along with SDA as the clock for the data.

As inputs for the bidirectional serial clock, these signals operate as described below.

State

Meaning

Asserted/Negated—The I2C unit uses this signal to synchronize incoming data on SDA.

The bus is assumed to be busy when this signal is detected low.

SDA

I/O

Serial data. Performs as an input when the MPC8540 is in a receiving mode. SDA also performs

as an output signal when the MPC8540 is transmitting (as an I2C master or a slave).

As outputs for the bidirectional serial data, these signals operate as described below.

State

Meaning

Asserted/Negated— Data is driven.

As inputs for the bidirectional serial data, these signals operate as described below.

State

Meaning

Asserted/Negated—Used to receive data from other devices. The bus is assumed to

be busy when SDA is detected low.

Table 11-3. I2C Memory Map

Address

I2C Register

Access

Reset

Section/Page

0x0_3000

I2CADR—I2C address register

R/W

0x00

11.3.1.1/11-5

0x0_3004

I2CFDR—I2C frequency divider register

R/W

0x00

11.3.1.2/11-5

0x0_3008

I2CCR—I2C control register

R/W

0x00

11.3.1.3/11-6

0x0_300C

I2CSR—I2C status register

R/W

0x81

11.3.1.4/11-7

0x0_3010

I2CDR—I2C data register

R/W

0x00

11.3.1.5/11-9

0x0_3014

I2CDFSRR—I2C digital filter sampling rate register

R/W

0x10

11.3.1.6/11-10

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