MPC8540 datasheet(464/1302 Pages) FREESCALE

464 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-10

Freescale Semiconductor

I2C Interface

11.3.1.6

Digital Filter Sampling Rate Register (I2CDFSRR)

The digital filter sampling rate register (I2CDFSRR) is shown in Figure 11-7.

Figure 11-7. I2C Digital Filter Sampling Rate Register (I2CDFSRR)

Table 11-9 shows the field descriptions for I2CDFSRR.

11.4 Functional Description

The I

2C unit always performs as a slave receiver as a default, unless explicitly programmed to be

a master or slave transmitter. After the boot sequencer has completed (when powered up in boot

sequencer mode), the I

2C interface will perform as a slave receiver.

11.4.1

Transaction Protocol

A standard I2C transfer consists of the following:

•

START condition

•

Slave target address transmission

•

Data transfer

•

STOP condition

Figure 11-8 shows the interaction of these four parts with the calling address, data byte, and new

calling address components of the I

2C protocol. The details of the protocol are described in the

following subsections.

DFSR

Reset

0001_0000

Offset

0x0_3014

Table 11-9. I2CDFSRR Field Descriptions

Bits Name

Description

0–1

—

Reserved

2–7 DFSR Digital filter sampling rate. To assist in filtering out signal noise, the sample rate is programmed. This field

is used to prescale the frequency at which the digital filter takes samples from the I2C bus. The resulting

sampling rate is calculated by dividing the platform (CCB clock) frequency by the non-zero value of

DFSR. If I2CDFSRR is set to zero, the I2C bus sample points default to the reset divisor 0x10.

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