MPC8540 datasheet(465/1302 Pages) FREESCALE

465 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-11

Figure 11-8. I2C Interface Transaction Protocol

11.4.1.1

START Condition

When the I

2C bus is not engaged (both SDA and SCL lines are at logic high), a master can initiate

a transfer by sending a START condition. As shown in Figure 11-8, a START condition is defined

as a high-to-low transition of SDA while SCL is high. This condition denotes the beginning of a

new data transfer. Each data transfer can contain several bytes and awakens all slaves. The START

condition is initiated by a software write that sets I2CCR[MSTA].

11.4.1.2

Slave Address Transmission

The first byte of data is transferred by the master immediately after the START condition is the

slave address. This is a seven-bit calling address followed by a R/W bit, which indicates the

direction of the data being transferred to the slave. Each slave in the system has a unique address.

In addition, when the I

2C module is operating as a master, it must not transmit an address that is

the same as its slave address. An I2C device cannot be master and slave at the same time.

Only the slave with a calling address that matches the one transmitted by the master responds by

returning an acknowledge bit (pulling the SDA signal low at the 9th clock) as shown in

Figure 11-8. If no slave acknowledges the address, the master should generate a STOP condition

or a repeated START condition.

When slave addressing is successful (and SCL returns to zero), the data transfer can proceed on a

byte-to-byte basis in the direction specified by the R/W bit sent by the calling master.

567

A5 A6 R/W

D0 D1 D2 D3 D4 D5 D6

SCL

SDA

START

STOP

ack

Read/

write

Calling address

Data byte

A3 A4

A5 A6 R/W

SCL

SDA

START

STOP

Ack

ack

Read/

write

Calling address

New calling address

Repeat

START

Ack

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