MPC8540 datasheet(476/1302 Pages) FREESCALE

476 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

11-22

Freescale Semiconductor

I2C Interface

I2CSR[MIF] (or any other I2CSR bits), software delays may be needed in order to give the I

signals sufficient time to settle.

During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to

determine the direction of the subsequent transfer and I2CCR[MTX] should be programmed

accordingly. For slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and

I2CCR[MTX] must be read to determine the direction of the current transfer. See Section 11.5.8,

“Interrupt Service Routine Flowchart,” for more details.

11.5.4

Generation of STOP

A data transfer ends with a STOP condition generated by the master device. A master transmitter

can generate a STOP condition after all the data has been transmitted.

If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not

acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CCR[TXAK]))

before reading the next-to-last byte of data. At this time, the next-to-last byte of data has already

been transferred on the I

2C interface, so the last byte will not receive the data acknowledge

(because I2CCR[TXAK] is set). For 1-byte transfers, a dummy read should be performed by the

interrupt service routine (see Section 11.5.8, “Interrupt Service Routine Flowchart”). Before the

interrupt service routine reads the last byte of data, a STOP condition must first be generated.

The I2C controller automatically generates a STOP if I2CCR[TXAK] is set. Therefore,

I2CCR[TXAK] must be set before allowing the I

2C module to receive the last data byte on the I2C

bus. Eventually, I2CCR[TXAK] needs to be cleared again for subsequent I2C transactions. This

can be accomplished when setting up the I2CCR for the next transfer.

11.5.5

Generation of Repeated START

At the end of a data transfer, if the master still wants to communicate on the bus, it can generate

another START condition followed by another slave address without first generating a STOP

condition. This is accomplished by setting I2CCR[RSTA].

11.5.6

Generation of SCL When SDA Low

It is sometimes necessary to force the I

2C module to become the I2C bus master out of reset and

drive SCL (even though SDA may already be driven, which indicates that the bus is busy). This

can occur when a system reset does not cause all I

2C devices to be reset. Thus, SDA can be driven

low by another I

2C device while this I2C module is coming out of reset and will stay low

indefinitely. The following procedure can be used to force this I

2C module to generate SCL so that

the device driving SDA can finish its transaction:

1. Disable the I2C module and set the master bit by setting I2CCR to 0x20

2. Enable the I

2C module by setting I2CCR to 0xA0

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