MPC8540 datasheet(477/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

11-23

3. Read the I2CDR

4. Return the I2C module to slave mode by setting I2CCR to 0x80

11.5.7

Slave Mode Interrupt Service Routine

In the slave interrupt service routine, the module addressed as a slave should be tested to check if

a calling of its own address has been received. If I2CSR[MAAS] is set, software should set the

transmit/receive mode select bit (I2CCR[MTX]) according to the R/W command bit

(I2CSR[SRW]). Writing to I2CCR clears MAAS automatically. MAAS is read as set only in the

interrupt handler at the end of that address cycle where an address match occurred; interrupts

resulting from subsequent data transfers clear MAAS. A data transfer can then be initiated by

writing to I2CDR for slave transmits or dummy reading from I2CDR in slave-receive mode. The

slave drives SCL low between byte transfers. SCL is released when the I2CDR is accessed in the

required mode.

11.5.7.1

Slave Transmitter and Received Acknowledge

In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested

before sending the next byte of data. The master signals an end-of-data by not acknowledging the

data transfer from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave

transmitter interrupt routine must clear I2CCR[MTX] to switch the slave from transmitter to

receiver mode. A dummy read of I2CDR then releases SCL so that the master can generate a STOP

condition. See Section 11.5.8, “Interrupt Service Routine Flowchart.”

11.5.7.2

Loss of Arbitration and Forcing of Slave Mode

When a master loses arbitration the following conditions all occur:

•

I2CSR[MAL] is set

•

I2CCR[MSTA] is cleared (changing the master to slave mode)

•

An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer

Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear

it if it is set. See Section 11.4.2.1, “Arbitration Control,” for more information.

11.5.8

Interrupt Service Routine Flowchart

Figure 11-11 shows an example algorithm for an I

2C interrupt service routine. Deviation from the

flowchart may result in unpredictable I

2C bus behavior. However, in the slave receive mode (not

shown), the interrupt service routine may need to set I2CCR[TXAK] when the next-to-last byte is

to be accepted. It is recommended that an msync instruction follow each I

2C register read or write

to guarantee in-order instruction execution.

MPC8540 Datasheet(PDF) 477 Page - Freescale Semiconductor, Inc

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