MPC8540 datasheet(450/1302 Pages) FREESCALE

450 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-46

Freescale Semiconductor

Programmable Interrupt Controller

10.4.1.3 Interrupt Acknowledge

The PIC unit notifies the processor core of an interrupt by asserting the int signal. When the

processor core acknowledges the interrupt request by reading the interrupt acknowledge register

(IACK) in the PIC unit, the PIC returns the 16-bit vector associated with the interrupt source to

the processor. The interrupt is then considered to be in-service, and remains in-service until the

processor performs a write to the PIC unit end of interrupt register (EOI). Writing to the EOI is

referred to as an EOI cycle.

10.4.2 Nesting of Interrupts

If the processor is servicing an interrupt, it can only be interrupted again if the PIC receives an

interrupt request from a source with higher priority than the one currently being serviced. This is

true even if software, as part of its interrupt service routine, writes a new and lower value into the

CTPR.

Thus, although several interrupts may be in-service simultaneously, the code currently executing

is always handling the highest priority of all the interrupts that are in service. When the processor

performs an EOI cycle, this highest priority interrupt is taken out-of-service. The next EOI cycle

takes the next-highest priority interrupt out-of-service, and so on. An interrupt with lower priority

than those currently in-service is not started until all higher priority interrupts complete even if its

priority is greater than the CTPR value.

10.4.3 Processor Initialization

The processor can reset itself by writing to the processor initialization register (PIR). This causes

the assertion of the core_reset output signal. When this occurs, the processor also gets written to

0x000F to disable the delivery of any interrupts.

10.4.4 Spurious Vector Generation

Under certain circumstances, the PIC has no valid vector to return to the processor during an

interrupt acknowledge cycle. In these cases, the spurious vector from the spurious vector register

is returned. The following cases cause a spurious vector fetch:

•

int is asserted in response to an externally sourced interrupt that is activated with

level-sensitive logic and the source negates before the interrupt is acknowledged.

•

int is asserted for an interrupt source that is later masked (using the mask bit in the

corresponding vector/priority register) before the interrupt is acknowledged.

•

int is asserted for an interrupt source that is later masked by an increase in the task priority

level before the interrupt is acknowledged.

•

An interrupt acknowledge cycle is performed by the processor in spite of the fact that the

PIC did not assert the int signal.

MPC8540 Datasheet(PDF) 450 Page - Freescale Semiconductor, Inc

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