MPC8540 datasheet(447/1302 Pages) FREESCALE

447 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-43

10.4 Functional Description

This section is a functional description of the PIC.

10.4.1 Flow of Interrupt Control

Figure 10-37 is a block diagram of the PIC unit showing the flow of interrupt processing. This

figure is intended to aid in understanding and does not fully represent all internal circuitry of the

actual implementation. The PIC receives interrupt signals from both external and internal sources.

These signals are qualified and latched in the interrupt pending register (IPR). The IPR feeds the

interrupt selector (IS). The interrupt router of the PIC monitors the outputs of its internal interrupt

request register (IRR) and other configuration registers. When the priority of the interrupt latched

in the IRR is higher than the value in the processor’s task priority register, the interrupt router

asserts the internal interrupt signal (int) to indicate an interrupt request to the processor. This

causes the processor to vector to the external interrupt handler.

Note that the IPR, IS, and IRR are internal registers that are not accessible to the programmer.

MPC8540 Datasheet(PDF) 447 Page - Freescale Semiconductor, Inc