MPC8540 datasheet(444/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-40

Freescale Semiconductor

Programmable Interrupt Controller

Table 10-37 describes the IPIDRn fields.

10.3.7.2 Processor Current Task Priority Register (CTPR)

There is one CTPR on this device (MPC8540) shown in Figure 10-33. Software must write the

priority of the current processor task in the CTPR. The PIC uses this value for comparison with

the priority of incoming interrupts. Given several concurrent incoming interrupts, the highest

priority interrupt is asserted to the core if the following apply:

•

The interrupt is not masked

•

The priority of the interrupt is higher than the values in the CTPR and ISR

Priority levels from 0 (lowest) to 15 (highest) are supported. Setting the task priority to 15 masks

all external interrupts signaled through the int signal. Hardware sets CTPR to 0x0000_000F during

reset or when the Px field of the processor initialization register is set. This effectively prevents

the PIC from signaling any interrupts through the int signal.

Figure 10-33. Processor Current Task Priority Register (CTPR)

Table 10-38 describes the CTPR.

Table 10-37. IPIDRn Field Descriptions

Bits

Name

Description

0–30

—

Reserved

Processor 0. Determines if processor 0 receives the interrupt. Write only.

0 Processor 0 does not receive the interrupt.

1 Directs the interrupt to processor 0.

27 28

R 0000000000

000000000000

000000

TASKP

Reset

0000_0000_0000_0000_0000_0000_0000_1111

Offset

0x6_0080 (see Section 10.3.7, “Per-CPU Registers.”)

Table 10-38. CTPR Field Descriptions

Bits

Name

Description

0–27

—

Reserved

28–31

TASKP Task priority. This field is set from 0 to 15, where 15 corresponds to the highest priority for processor

tasks. If CTPR[TASKP] = 0xF, no interrupts are signaled to the processor.

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