MPC8540 datasheet(448/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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448 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-44

Freescale Semiconductor

Programmable Interrupt Controller

Figure 10-37. PIC Interrupt Processing Flow Diagram

The interrupt handler executing on the processor should then acknowledge the interrupt by

explicitly reading IACK (at which point the interrupt is considered to be in-service). The PIC unit

interprets this read as an interrupt acknowledge (IACK) cycle; in response, the PIC unit returns the

Interrupt Pending Register

Internal, External, and

Interrupt Selector

In-Service Register

int

IACK

EOI

cint

Mask

Critical Interrupt xIDR[CI]

External Pin xIDR[EP]

IRQ_OUT

Global Timers

(4)

Inter-Processor

Message Interrupts

(IS)

To Processor Core

Note: All signal lines represent buses except for int, cint, and IRQ_OUT.

The behavior of the PIC unit is not defined if both the EP and CI bits of the same interrupt

destination register are set.

Interrupt Router

To Processor Core

End of Interrupt

Highest Priority

Interrupt

(ISR)

Processor’s Task Priority

Interrupt Request Register

Pipeline Latch

(IRR)

Activity Bit

(IPR)

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