MPC8540 datasheet(451/1302 Pages) FREESCALE

451 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-47

In all cases, a spurious vector is not returned if another pending interrupt has sufficient priority to

interrupt the processor. If such an interrupt is available, the vector for that source is returned. The

EOI register should not be written in response to the spurious vector. Otherwise, a

previously-accepted interrupt might be cleared unintentionally.

10.4.5 Messaging Interrupts

There are four 32-bit message registers that can be used to send 32-bit messages to the processor.

A messaging interrupt is generated by writing a message register if the corresponding enable bit

in the message enable/status register is set, and the interrupt is not masked. Reading the message

10.4.6 Global Timers

There are appropriate clock prescalers and synchronizers to provide a time base for the four

internal timers of the PIC unit. The timers can be individually programmed to generate a processor

interrupt when they count down to zero and can be used to generate regular periodic interrupts.

Each timer has the following four configuration and control registers:

•

Global timer current count register (GTCCRn)

•

Global timer base count register (GTBCRn)

•

Global timer vector-priority register (GTVPRn)

•

Global timer destination register (GTDRn)

The timer frequency should be written to the TFRR. (All of the timers operate at this frequency.)

Refer to Section 10.3.2.1, “Timer Frequency Reporting Register (TFRR),” for a description of this

Timer interrupts are all edge-triggered interrupts. If a timer period expires while a previous

interrupt from the same source is pending or in-service, the subsequent interrupt is lost.

The timer control register (TCR) provides users with the ability to create timers larger than the

31-bit global timers. The option also exists to change the timer frequency by setting the

appropriate fields of the TCR. See Section 10.3.2.6, “Timer Control Register (TCR).”

10.4.7 Reset of the PIC

The PIC unit is reset by a device power-on reset (POR) or by software that sets the GCR[RST] bit.

Both of these actions cause the following:

•

All pending and in-service interrupts are cleared.

•

All interrupt mask bits are set.

MPC8540 Datasheet(PDF) 451 Page - Freescale Semiconductor, Inc