MPC8540 datasheet(438/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-34

Freescale Semiconductor

Programmable Interrupt Controller

Table 10-31 describes the EIDR fields. Because external interrupts can be channeled only to

processor 0, the P0 bit is permanently set. As shown in Figure 10-37, if either the CI or EP bits are

set, the interrupt is not sent to the processor’s interrupt input.

The EP or CI fields must be set only for level-sensitive interrupts. Setting these fields for

edge-sensitive interrupts does not provide reliable interrupt response.

10.3.6.3 Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR31)

The internal interrupt vector/priority registers (IIVPRn), shown in Figure 10-27, have the same

fields and format as the GTVPRn, except that they apply to the internal interrupt sources listed in

Table 10-4. These interrupts are all level-sensitive.

NOTE

Because all internal interrupts are active-high, clearing any IIVPRn

polarity field disables that interrupt. Care should be taken to ensure

this field is not inadvertently corrupted when loading or reloading

IIVPRs with priority, mask, or vector data.

Figure 10-27. Internal Interrupt Vector/Priority Registers (IIVPRn)

Table 10-31. EIDRn Field Descriptions

Bits

Name

Description

External pin. Allows external interrupt to be serviced externally.

0 External interrupt is serviced internally with int signal to the processor core.

1 External interrupt is directed to IRQ_OUT for external service.

Critical interrupt.

0 External interrupt is serviced internally with int signal to the processor core.

1 External interrupt is directed to the processor 0 as a critical interrupt with the cint signal.

2–30

—

Reserved

Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core

device. Because the MPC8540 is a single-core device, all interrupts that are serviced internally are

always directed to processor 0. Permanently set and read only.

1 Interrupt directed to processor 0.

11 12

15 16

MSK

A 0000

000

PRIORITY

VECTOR

Reset

1000_0000_1000_0000_0000_0000_0000_0000

Offset

IIVPR0–7: 0x5_0200, 0x5_0220, 0x5_0240, 0x5_0260, 0x5_0280, 0x5_02A0, 0x5_02C0, 0x5_02E0

IIVPR8–15: 0x5_0300, 0x5_0320, 0x5_0340, 0x5_0360, 0x5_0380, 0x5_03A0, 0x5_03C0, 0x5_03E0

IIVPR16–23: 0x5_0400, 0x5_0420, 0x5_0440, 0x5_0460, 0x5_0480, 0x5_04A0, 0x5_04C0, 0x5_04E0

IIVPR24–31: 0x5_0500, 0x5_0520, 0x5_0540, 0x5_0560, 0x5_0580, 0x5_05A0, 0x5_05C0, 0x5_05E0

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