MPC8540 datasheet(412/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-8

Freescale Semiconductor

Programmable Interrupt Controller

10.2 External Signal Descriptions

The following sections provide an overview and detailed descriptions of the PIC signals.

10.2.1 Signal Overview

PIC interface signals are described in Table 10-5. There are 12 distinct external interrupt request

input signals (IRQ[0:11]) and 1 interrupt request output signal (IRQ_OUT). As Table 10-5 shows,

three IRQ inputs are multiplexed with DMA signals for DMA channel 3.

10.2.2 Detailed Signal Descriptions

Table 10-6 provides detailed descriptions of the external PIC signals.

Table 10-5. PIC Interface Signals

Signal Name

I/O

Description

IRQ[0:8]

External interrupts

IRQ9/DMA_DREQ31

1 IRQ9–IRQ11 are multiplexed with DMA3 signals. These functions are mutually exclusive; the active function is

specified in PMUXCR of the global utilities block as described in Section 18.4.1.10, “Alternate Function Signal

Multiplex Control Register (PMUXCR).”

External interrupt/DMA channel 3 request

IRQ10/DMA_DACK31

I or O

External interrupt (input)/DMA channel 3 acknowledge (output)

IRQ11/DMA_DDONE31

I or O

External interrupt (input)/DMA channel 3 done (output)

IRQ_OUT

Interrupt request out

MCP

Processor machine check

UDE

Unconditional debug event

Table 10-6. Interrupt Signals—Detailed Signal Descriptions

Signal

Description

IRQ[0:11]

Interrupt request 0–11. The polarity and sense of each of these signals is programmable. All of these

inputs can be driven completely asynchronously.

State

Meaning

Asserted—When an external interrupt signal is asserted (according to the programmed

polarity), the priority is checked by the PIC unit, and the interrupt is conditionally passed

to the processor. In pass-through mode, only interrupts detected on IRQ0 are passed

directly to the processor core.

Negated—There is no incoming interrupt from that source.

Timing Assertion—All of these inputs can be asserted completely asynchronously.

Negation—Interrupts programmed as level-sensitive must remain asserted until serviced.

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