MPC8540 datasheet(413/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-9

10.3 Memory Map/Register Definition

The PIC programmable register map occupies 256 Kbytes of memory-mapped space. Reading

undefined portions of the memory map returns all zeros; writing has no effect.

All PIC registers are 32 bits wide and, although located on 128-bit address boundaries, should only

be accessed as 32-bit quantities.

IRQ_OUT

O Interrupt request out. Active-low, open drain. When the PIC is programmed in pass-through mode, this

output reflects the raw interrupts generated by on-chip sources. See Section 10.1.4, “Modes of

Operation,” for more details.

State

Meaning

Asserted—At least one interrupt is currently being signalled to the external system.

Negated—Indicates no interrupt source currently routed to IRQ_OUT.

Timing Because external interrupts are asynchronous with respect to the system clock, both

assertion and negation of IRQ_OUT occurs asynchronously with respect to the interrupt

source. All timing given here is approximate.

Assertion—Internal interrupt source: 2 CCB clock cycles after interrupt occurs.

External interrupt source: 4 cycles after interrupt occurs.

Message interrupts: 2 cycles after write to message register.

Negation—Follows interrupt source negation with the following delay:

Internal interrupt: 2 CCB clock cycles

External interrupt: 4 cycles.

Message interrupts: 2 cycles after message register cleared.

MCP

Machine check processor. Assertion causes a machine check interrupt to the e500 core. Note that if the

e500 core is not configured to process machine check interrupts (MSR[ME] = 0), assertion of MCP

causes a checkstop condition. Note that internal sources for the internal core_mcp signal can also cause

a machine check interrupt to the processor core, as described in Section 18.4.1.13, “Machine Check

Summary Register (MCPSUMR),” Table 10-2 and Table 10-3.

State

Meaning

Asserted—The MPC8540 should initiate a machine check interrupt or enter the checkstop

state as directed by the MSR.

Negated—Machine check handling is not being requested by the external system.

Timing Assertion—May occur at any time, asynchronous to any clock.

Negation—Because MCP is edge-triggered, it can be negated one clock after its assertion.

UDE

Unconditional debug event. Assertion signal causes an unconditional debug exception to the e500 core.

State

Meaning

Asserted—Indicates that the MPC8540 should initiate an unconditional debug event interrupt

to the processor core.

Negated—Indicates that unconditional debug event handling is not being requested by UDE.

Timing Assertion—May occur at any time, asynchronous to any clock.

Negation—Should remain asserted until software in the unconditional debug event interrupt

handler causes the external device asserting the UDE signal to negate it.

Table 10-6. Interrupt Signals—Detailed Signal Descriptions (continued)

Signal

Description

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