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MPC8540 Datasheet(PDF) 384 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 384 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
9-30
Freescale Semiconductor
DDR Memory Controller
Section 9.5.12, “Error Management,” explains how the DDR memory controller handles errors.
9.5.1
DDR SDRAM Interface Operation
The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs
with different sizes can be used in the same system. Fourteen multiplexed address signals and two
logical bank select signals support device densities from 64 Mbit to 1 Gbit. Four chip select (CS)
signals support up to two DIMMs of memory. The DDR SDRAM physical banks can be built from
standard memory modules or directly-attached memory devices. The data path to individual
physical banks is 64 bits wide, 72 bits with ECC. The MPC8540 DDR memory controller supports
physical bank sizes from 32 Mbytes to 1 Gbytes. The physical banks can be constructed using
×8,
or
×16 memory devices. The memory technologies supported are 64, 128, 256, and 512 Mbit, and
1 Gbit. Nine data qualifier (DQM) signals provide byte selection for memory accesses.
NOTE
An 8-bit DDR SDRAM device has a DQM signal and 8 data signals
(DQ[0:7]). A 16-bit DDR SDRAM device has 2 DQM signals
associated with specific halves of the 16 data signals (DQ[0:7] and
DQ[8:15]).
When ECC is enabled, all memory accesses are performed on double-word boundaries (that is, all
DQM signals are set simultaneously). However, when ECC is disabled, the memory system uses
the DQM signals for byte lane selection.
Table 9-25 shows the DDR memory controller’s relationships between data byte lane 0–7,
MDM[0:7], MDQS[0:7], and MDQ[0:63].
Table 9-25. Byte Lane to Data Relationship
Data Byte Lane Data Bus Mask
Data Bus
Strobe
Data Bus 64-Bit
Mode
0 (MSB)
MDM[0]
MDQS[0]
MDQ[0:7]
1
MDM[1]
MDQS[1]
MDQ[8:15]
2
MDM[2]
MDQS[2]
MDQ[16:23]
3
MDM[3]
MDQS[3]
MDQ[24:31]
4
MDM[4]
MDQS[4]
MDQ[32:39]
5
MDM[5]
MDQS[5]
MDQ[40:47]
6
MDM[6]
MDQS[6]
MDQ[48:55]
7 (LSB)
MDM[7]
MDQS[7]
MDQ[56:63]



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