MPC8540 datasheet(381/1302 Pages) FREESCALE

381 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-27

ACTIVE command followed by a READ or WRITE. (Accessing open pages does not require an

ACTIVE command.) The address bits registered coincident with the activate command specifies

the logical bank and row to be accessed. The address coincident with the READ or WRITE

command specify the logical bank and starting column for the burst access.

The data interface is source synchronous, meaning whatever sources the data also provides a

clocking signal to synchronize data reception. These bidirectional data strobes (MDQS[0:8]) are

inputs to the controller during reads, and outputs during writes. The DDR SDRAM specification

requires the data strobe signals to be centered within the data tenure during writes and to be offset

by the controller to the center of the data tenure during reads. This is implemented in the controller

with delay chains for the data strobe signals during reads and a delay chain on the data multiplexer

select during writes.

When ECC is enabled, one clock cycle is added to the read path to check ECC and correct

single-bit errors. ECC generation does not add a cycle to the write path.

Figure 9-22 shows how the on-chip DLL can be used with the memory controller.

Figure 9-22. Controller DLL Timing Loop

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DLL

DDR Controller

DLL_Sync_Out

DDR SDRAM

Internal Clock

DLL

DLL_Sync_In

DLL timing

loop

Clock PCB Trace Length “L”

MPC8540 Datasheet(PDF) 381 Page - Freescale Semiconductor, Inc