MPC8540 datasheet(377/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-23

Table 9-21 describes the ERR_INT_EN fields.

9.4.1.17 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)

The memory error attributes capture register, shown in Figure 9-18, sets attributes for errors

including type, size, source, and others.

Figure 9-18. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)

Table 9-22 describes the CAPTURE_ATTRIBUTES fields.

Table 9-21. ERR_INT_EN Field Descriptions

Bits

Name

Description

0–27

—

Reserved

MBEE Multiple-bit ECC error interrupt enable. Note that uncorrectable read errors may cause the assertion of

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] must be zero and

MBEE and DDR_SDRAM_CFG[ECC_EN] must be set to ensure that an interrupt is generated. For more

information, see Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

0 Multiple-bit ECC errors cannot generate interrupts.

1 Multiple-bit ECC errors generate interrupts.

SBEE Single-bit ECC error interrupt enable

0 Single-bit ECC errors cannot generate interrupts.

1 Single-bit ECC errors generate interrupts.

—

Reserved

MSEE Memory select error interrupt enable

0 Memory select errors do not cause interrupts.

1 Memory select errors generate interrupts.

10 11

15 16 17181920

BNUM

TSIZ

TSRC

TTYP

0000

000

VLD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E4C

Table 9-22. CAPTURE_ATTRIBUTES Field Descriptions

Bits

Name

Description

0—

Reserved

1–3

BNUM Data beat number. Captures the data beat number for the detected error. Relevant only for ECC errors.

4—

Reserved

5–7

TSIZ

Transaction size for the error. Captures the transaction size in double words.

8–10

—

Reserved

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