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MPC8540 Datasheet(PDF) 376 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 376 Page - Freescale Semiconductor, Inc |
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376 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 9-22 Freescale Semiconductor DDR Memory Controller Figure 9-16. Memory Error Disable Register (ERR_DISABLE) Table 9-20 describes the ERR_DISABLE fields. 9.4.1.16 Memory Error Interrupt Enable (ERR_INT_EN) The memory error interrupt enable register, shown in Figure 9-17, enables ECC interrupts or memory select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the programmable interrupt controller (PIC). Figure 9-17. Memory Error Interrupt Enable Register (ERR_INT_EN) 0 27 28 29 30 31 R 0000000000000000000000000000 MBED SBED 0 MSED W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x0_2E44 Table 9-20. ERR_DISABLE Field Descriptions Bits Name Description 0–27 — Reserved 28 MBED Multiple-bit ECC error disable 0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if ERR_INT_EN[MBEE] is set. Note that uncorrectable read errors cause the assertion of core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBED must be zero and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure that an interrupt is generated. 1 Multiple-bit ECC errors are not detected or reported. 29 SBED Single-bit ECC error disable 0 Single-bit ECC errors are enabled. 1 Single-bit ECC errors are disabled. 30 — Reserved 31 MSED Memory select error disable 0 Memory select errors are enabled. 1 Memory select errors are disabled. 0 27 28 29 30 31 R 0000000000000000000000000000 MBEE SBEE 0 MSEE W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x0_2E48 |
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