MPC8540 datasheet(375/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-21

9.4.1.14 Memory Error Detect (ERR_DETECT)

The memory error detect register, shown in Figure 9-15, stores the detection bits for multiple

memory errors, single- and multiple-bit ECC errors, and memory select errors. It is a read/write

type of memory error by examining the contents of this register. If an error is disabled with

ERR_DISABLE, the corresponding error is never detected or captured in ERR_DETECT.

Table 9-19 describes the ERR_DETECT fields.

9.4.1.15 Memory Error Disable (ERR_DISABLE)

The memory error disable register, shown in Figure 9-16, allows selective disabling of the DDR

controller’s error detection circuitry. Disabled errors are not detected or reported.

MME

000000000000000000000000000

MBE SBE

MSE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E40

Figure 9-15. Memory Error Detect Register (ERR_DETECT)

Table 9-19. ERR_DETECT Field Descriptions

Bits

Name

Description

MME

Multiple memory errors. This bit is cleared by software writing a 1.

0 Multiple memory errors of the same type were not detected.

1 Multiple memory errors of the same type were detected.

1–27

—

Reserved

MBE

Multiple-bit error. This bit is cleared by software writing a 1.

0 A multiple-bit error has not been detected.

1 A multiple-bit error has been detected.

SBE

Single-bit ECC error. This bit is cleared by software writing a 1.

0 The number of single-bit ECC errors detected has not crossed the threshold set in ERR_SBE[SBET].

1 The number of single-bit ECC errors detected crossed the threshold set in ERR_SBE[SBET].

—

Reserved

MSE

Memory select error. This bit is cleared by software writing a 1.

0 A memory select error has not been detected.

1 A memory select error has been detected.

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