MPC8540 datasheet(382/1302 Pages) FREESCALE

382 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-28

Freescale Semiconductor

DDR Memory Controller

Figure 9-23 shows an example DDR SDRAM configuration with four physical banks.

Figure 9-23. Typical Dual Data Rate SDRAM Internal Organization

Figure 9-24 shows some typical signal connections.

Figure 9-24. Typical DDR SDRAM Interface Signals

Figure 9-25 shows an example DDR SDRAM configuration with four physical banks each

comprised of nine 8M

× 8 DDR modules for a total of 256 Mbytes of system memory. One of the

nine modules is used for the memory’s ECC checking function. Certain address and control lines

may require buffering. Analysis of the MPC8540 device’s AC timing specifications, desired

memory operating frequency, capacitive loads, and board routing loads, can assist the system

designer in deciding signal buffering requirements. The MPC8540 DDR memory controller drives

15 address pins, but in this example the DDR SDRAM devices use only 12 bits.

Logical

Bank 0

Logical

Bank 1

Logical

Bank 2

Logical

Bank 3

MUX, MASK,

Read Data Latch

Data-out Registers

Data-in Registers

Data Bus

ADDR

COMMAND:

DQM

BA1,BA0

CKE, MCK, MCK

MCS, MRAS, MCAS, MWE

Control

SDRAM

A[12:0]

Write Enable

DQ[7:0]

DQS

64M

× 1 byte

Command

Bus

512 Mbit

BA[1:0]

DATA

ADDR

MRAS

MCAS

MWE

MCS

CKE

MCK

‘SUB’

BANK ADDR

STROBE

MPC8540 Datasheet(PDF) 382 Page - Freescale Semiconductor, Inc

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