MPC8540 datasheet(350/1302 Pages) FREESCALE

350 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

8-8

Freescale Semiconductor

e500 Coherency Module

8.2.1.6

ECM Error Address Capture Register (EEADR)

The ECM error address capture register (EEADR) is shown in Figure 8-7.

Figure 8-7. ECM Error Address Capture Register (EEADR)

Table 8-7 describes EEADR fields.

11–15

SRC_ID

Source ID. Specifies the source device mastering the transaction.

00000 PCI/PCI-X interface

00001–01001 Reserved

01010 Boot sequencer

01011

Reserved

01100

RapidIO

01101–01111 Reserved

10000 Processor (instruction)

10001 Processor (data)

10010 Reserved

10011

Reserved

10100 Reserved

10101 DMA

10110

Reserved

10111

SAP

11000

TSEC1

11001

TSEC2

11010

10/100 FEC

11011

Reserved

11100

RapidIO message units

11101

RapidIO doorbell units

11110

RapidIO port-write units

11111

Reserved

—

Reserved

17–20

TTYPE

Transaction type. Defined as follows:

0000 Write

0001 Reserved

0010 Write with allocate

0011 Write with allocate with lock

0100 Address only transaction

0101–0111 Reserved

1000 Read

1001 Read with unlock

101x Reserved

1100 Read with clear atomic

1101 Read with set atomic

1110 Read with decrement atomic

1111 Read with increment atomic

21–30

—

Reserved

VAL

0 ECM error attribute capture register does not contain valid information.

1 ECM error attribute capture register contains valid information.

ADDR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_1E10

Table 8-7. EEADR Field Descriptions

Bits

Name

Description

0–31

ADDR

Address. Specifies the 32-bit address of the transaction. Qualified by EEATR[VAL].

Table 8-6. EEATR Field Descriptions (continued)

Bits

Name

Description

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