MPC8540 datasheet(346/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

8-4

Freescale Semiconductor

e500 Coherency Module

8.2.1.2

ECM CCB Port Configuration Register (EEBPCR)

The ECM CCB port configuration register (EEBPCR) is shown in Figure 8-3.

Figure 8-3. ECM CCB Port Configuration Register (EEBPCR)

Table 8-3 describes EEBPCR fields.

CORE_STRM_DIS With A_STRM_DIS, controls whether the e500 core can stream commands onto the

CCB. A_STRM_DIS and CORE_STRM_DIS must both be cleared for the e500 core to

be enabled to stream address tenures that it masters.

0 Stream address tenures initiated by the e500 core, provided A_STRM_DIS is cleared.

1 Streaming of address tenures initiated by the e500 core not allowed.

30–31

A_STRM_CNT

Stream count. Specifies the maximum number of transactions that any master can stream

(issue sequentially without preemption) on the CCB following an initial transaction.

00 Reserved

01 One transaction can be streamed with the initial transaction.

10 Two transactions can be streamed with the initial transaction.

11 Three transactions can be streamed with the initial transaction. Default.

CPU_EN

CPU_PRI

Reset

0000_000n_0000_0000_0000_0000_0000_0000

Offset

0x0_1010

Table 8-3. EEBPCR Field Descriptions

Bits

Name

Description

0–6

—

Reserved

CPU_EN

CPU port enable. Controls boot holdoff mode when the device is an agent of an external host.

Specifies whether the e500 core (CPU) port is enabled to run transactions on the CCB. The CPU

boot configuration power-on reset pin (cfg_cpu_boot) determines the initial value of this bit. If the

pin is sampled as a logic 1 at the negation of reset, the CPU is enabled to boot at the end of the

POR sequence. Otherwise, the CPU cannot fetch its boot vector until an external host sets the

CPU_EN bit.

0 Boot holdoff mode. CPU arbitration is disabled on the CCB and no bus grants are issued.

1 CPU is enabled and receives bus grants in response to bus requests for the boot vector.

After this bit is set, it should not be cleared by software. It is not intended to dynamically enable

and disable CPU operation. It is only intended to end boot holdoff mode. See Section 4.4.3.5,

“CPU Boot Configuration,” for more information.

Table 8-2. EEBACR Field Descriptions (continued)

Bits

Name

Description

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