MPC8540 datasheet(344/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

8-2

Freescale Semiconductor

e500 Coherency Module

(CCB). This allows on-chip caches to snoop these transactions as if they were locally initiated and

to take actions to maintain coherency across cacheable memory.

8.1.2

Features

The ECM includes these distinctive features:

•

Support for e500 core and an L2/SRAM on the CCB, including a CCB arbiter. It sources a

64-bit data bus for returning read data from the ECM to the e500 core and routing write data

from the ECM to the L2/SRAM. It sinks a 128-bit data bus for receiving data from the

L2/SRAM and a 128-bit write data bus from the e500 core.

•

Four connection points for I/O initiating (mastering into the device) interfaces. One of those

connection points services OCeaN initiators, one services TSEC1, one services TSEC2,

and the last services other I/O initiators. The ECM supports five connection points for I/O

targets. The DDR memory controller, local bus, OCeaN targets, programmable interrupt

controller (PIC), and configuration register access block all have a target port connection

to the ECM.

•

Split transaction support—separate address and data tenures allow for pipelining of

transactions and out-of-order data tenures between initiators and targets.

•

Proper ordering of I/O-initiated transactions.

•

Speculative read bus for low-latency dispatch of reads to the DDR controller.

•

Low-latency path for returning read data from DDR to the e500.

•

Error registers trap transactions with invalid addresses. Errors can be programmed to

generate interrupts to the e500 core, as described in the following sections:

— Section 8.2.1.3, “ECM Error Detect Register (EEDR)”

— Section 8.2.1.4, “ECM Error Enable Register (EEER)”

— Section 8.2.1.5, “ECM Error Attributes Capture Register (EEATR)”

— Section 8.2.1.6, “ECM Error Address Capture Register (EEADR)”

•

Errors from I/O devices on reads (for example, a master-aborted read transaction on the PCI

interface) terminate with corrupt data sent to the requester. If the requester is the e500 core,

the ECM also asserts core_fault_in to the core, which causes the core to generate a machine

check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and one

of these errors occurs, appropriate interrupts must be enabled to ensure that an interrupt is

generated. See Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

8.2

Memory Map/Register Definition

Table 8-1 shows the ECM’s memory map. Undefined 4-byte address spaces within offset

0x000–0xFFF are reserved.

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