MPC8540 datasheet(338/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-34

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

7.10 Initialization/Application Information

This section describes some required steps for initializing the L2 SRAM both in L2 cache mode,

and in memory-mapped SRAM mode. Also, it includes some guidlines for error managment.

WWK

32-byte WWF

32-byte WWF atomic

I/E/EL/T

Miss in cache external write windows

E/EL

Hit in cache external write window. Set lock if

CEW lock attribute set

Same

EE/EL

TEL

I/E

Invalidate line

EL/T

Invalidate data, keep lock

< 32-byte WWF

< 32-byte WWF atomic

I/E

Miss in cache external write windows

EL/T

Miss in cache external write windows

I/T

Same

Hit in CEW window but need burst data

Same

Hit in cache external write window

E/EL

Hit in cache external write window. Set lock if

CEW lock attribute set

I/E

Invalidate line

EL/T

Invalidate data, keep lock

Read

Read atomic

I/T

Same

N/A

No L1/L2 effect

RWNITC

I/L/T

Same

Read-and-clear-lock

N/A

No L1/L2 effect

Kill

RWITM

RWITM atomic

RClaim

I/E

EL/T

Invalidate data, keep lock

I/E/EL/T

Same

Table 7-23. State Transitions Due to System-Initiated Transactions (continued)

Transaction Type

ci gbl

Initial L2

State

Final L2 State

Comments

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