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MPC8540 Datasheet(PDF) 323 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 323 Page - Freescale Semiconductor, Inc |
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323 / 1302 page ![]() Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 7-19 Figure 7-20 shows the L2 error attributes capture register (L2ERRATTR). Table 7-15 describes L2ERRATTR fields. 0 1 2 3 4 5 7 8 9 10 11 15 16 1718 1920 30 31 R0 0 DWNUM 0 TRANSSIZ BURST 00 TRANSSRC 00 TRANSTYPE 0 0 00 00 00 00 0 VALINFO W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x2_0E4C Figure 7-20. L2 Error Attributes Capture Register (L2ERRATTR) Table 7-15. L2ERRATTR Field Descriptions Bits Name Description 0–1 — Reserved 2–3 DWNUM Double-word number of the detected error (data ECC errors only) 4— Reserved 5–7 TRANSSIZ Transaction size for detected error Single-beat Burst 000 8 bytes Reserved 001 1 byte 16 bytes 010 2 bytes 32 bytes 011 3 bytes Reserved Single-beat Burst 100 4 bytes Reserved 101 5 bytes Reserved 110 6 bytes Reserved 111 7 bytes Reserved 8 BURST Burst transaction for detected error 0 Single-beat ( ≤ 64 bits) transaction 1 Burst transaction 9–10 — Reserved 11–15 TRANSSRC Transaction source for detected error 00000External (system logic) 10000Processor (instruction) 10001Processor (data) 16–17 — Reserved 18–19 TRANSTYP E Transaction type for detected error 00 Snoop (tag/status read) 01 Write 10 Read 11 Read-modify-write 20–30 — Reserved 31 VALINFO L2 capture registers valid 0 L2 capture registers contain no valid information or no enabled errors were detected. 1 L2 capture registers contain information of the first detected error which has reporting enabled. Software must clear this bit to unfreeze error capture so error detection hardware can overwrite the capture address/data/attributes for a newly detected error. |
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