MPC8540 datasheet(318/1302 Pages) FREESCALE

318 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-14

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Figure 7-12 shows the L2 error injection mask low register (L2ERRINJLO) fields.

Table 7-7 describes L2ERRINJLO[EIMASKLO].

Figure 7-13 shows the L2 error injection mask control register (L2ERRINJCTL).

Table 7-8 describes L2ERRINJCTL fields.

EIMASKLO

Reset

All zeros

Offset

0x2_0E04

Figure 7-12. L2 Error Injection Mask Low Register (L2ERRINJLO)

Table 7-7. L2ERRINJLO Field Description

Bits

Name

Description

0–3

EIMASKL

Error injection mask/low word. A set bit corresponding to a data path bit causes that bit on the data

path to be inverted on SRAM writes if L2ERRINJCTL[DERRIEN] = 1.

014

R 000 000 000 000 00 0

TERRIEN

000000

ECCMB DERRIEN

ECCERRIM

Reset

All zeros

Offset

0x2_0E08

Figure 7-13. L2 Error Injection Mask Control Register (L2ERRINJCTL)

Table 7-8. L2ERRINJCTL Field Descriptions

Bits

Name

Description

0–14

—

Reserved

TERRIEN

L2 tag array error injection enable

0 No tag errors are injected.

1 All subsequent entries written to the L2 tag array have the parity bit inverted.

16–21

—

Reserved

ECCMB

ECC mirror byte enable

0 ECC byte mirroring is disabled

1 The most significant data path byte is mirrored onto the ECC byte if DERRIEN = 1.

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