MPC8540 datasheet(316/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-12

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

L2SRBAR bits are described in Table 7-5.

When enabled, the windows defined in L2SRBARn supersede all other mappings of these

addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must

never overlap configuration space as defined by CCSRBAR (see Section 4.3.1.1.2,

“Configuration, Control, and Status Base Address Register (CCSRBAR)”). Overlapping SRAM

and local access windows is discouraged because processor and snoopable I/O transactions would

map to the SRAM while non-snooped I/O transactions would be mapped by the local access

windows. Only if all accesses to the SRAM address range are snoopable can results be consistent

if SRAM and local access windows overlap. Furthermore, L2SRBARn should not overlap a DDR

DRAM space for which a valid chip select is defined. This could result in spurious ECC errors if

ECC and speculative reads are enabled. See Section 2.2.3.7, “Illegal Interaction Between Local

Access Windows and DDR SDRAM Chip Selects.”

7.3.1.5

L2 Error Registers

L2 error detection, reporting, and injection allow flexible handling of ECC and parity errors in the

L2 data and tag arrays. When the MPC8540 detects an L2 error, the appropriate bit in the error

detect register (L2ERRDET) is set. Error detection is disabled by setting the corresponding bit in

the error disable register (L2ERRDIS).

The address and attributes of the first detected error are also saved in the error capture registers

(L2ERRADDR, L2ERRATTR, L2CAPTDATAHI, L2CAPTDATALO, and L2CAPTACC).

Subsequent errors set error bits in the error detection registers, but information is saved only for

the first one. Error reporting (by generating an interrupt) is enabled by setting the corresponding

bit in the error interrupt enable register (L2ERRINTEN). Note that the error detect bit is set

regardless of the state of the interrupt enable bit. When an error is detected, if error detection is

enabled the L2 cache/SRAM always asserts an internal error signal with read data to prevent the

L1 caches and architectural registers from being loaded with corrupt data. If error detection is

disabled, the detected error bit is not set and no internal signal is asserted.

The L2 error detect register (L2ERRDET) is implemented as a bit-reset type register. Reading

from this register occurs normally; however, write operations can clear but not set bits. A bit is

cleared whenever the register is written, and the data in the corresponding bit location is a 1. For

example, to clear bit 6 and not affect any other bits in the register, the value 0x0200_0000 is written

to the register.

Table 7-5. L2SRBARn Field Descriptions

Bits

Name

Description

0–17

ADDR

L2 memory-mapped SRAM base address

18–31

—

Reserved

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