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ADC358X Datasheet(PDF) 49 Page - Texas Instruments |
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ADC358X Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 85 page  8.3.5.4.1 Configuration Example The following is a step by step programming example to configure the ADC358x to complex decimation by 8 with 1-wire SLVDS and 16-bit output. 1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS) 2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse) 3. 0x19 0x80 (configure FCLK) 4. 0x1B 0x88 (select 16-bit output resolution) 5. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern) 6. 0x24 0x06 (enable decimation filter) 7. 0x25 0x30 (configure complex decimation by 8) 8. 0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency) 9. 0x27/0x2E 0x08 (configure Q-delay register bit) 10. 0x26 0xAA, 0x26 0x88(set digital mixer gain to 6-dB and toggle the mixer update) 8.3.5.5 Output Data Format The output data can be configured to two's complement (default) or offset binary formatting using SPI register writes (register 0x8F and 0x92). Table 8-9 provides an overview for minimum and maximum output codes for the two formatting options. The actual output resolution is set by the output bit mapper. Table 8-9. Overview of minimum and maximum output codes vs output resolution for different formatting Two's Complement (default) Offset Binary RESOLUTION (BIT) 14 16 18 20 14 16 18 20 VIN,MAX 0x1FFF 0x7FFF 0x1FFFF 0x7FFFF 0x3FFF 0xFFFF 0x3FFFF 0xFFFFF 0 0x0000 0x00000 0x2000 0x8000 0x20000 0x80000 VIN,MIN 0x2000 0x8000 0x20000 0x80000 0x0000 0x00000 8.3.6 Test Pattern In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as shown in Figure 8-49. In decimation mode (real and complex), the test patterns replace the output data of the DDC - however channel A controls the test patterns for both channels. N NCO TEST PATTERN Output Formatter 14/16/18/ 20-bit DIG I/F Output Bit Mapper Output Scrambler Figure 8-49. Test Pattern Generator • RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in RAMP pattern mode. – 00001: 18-bit output resolution – 00100: 16-bit output resolution – 10000: 14-bit output resolution • Custom Pattern: Configured in the CUSTOM PAT register www.ti.com ADC3581, ADC3582, ADC3583 SBAS873A – FEBRUARY 2021 – REVISED OCTOBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: ADC3581 ADC3582 ADC3583 |
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