6.5 Electrical Characteristics (continued)

TJ = –55°C to +125°C; typical values at TJ = 25°C, V(A) = V(OUT) = V(VS) = V(VSNS) = 12 V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,

V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(CAP UVLO)

Charge Pump UVLO voltage

threshold, rising

5.4

6.6

7.9

V

Charge Pump UVLO voltage

threshold, falling

4.4

5.5

6.6

V

IDEAL DIODE (A, C, DGATE)

V(A_PORR)

V(A) POR threshold, rising

2.2

2.35

2.6

V

V(A_PORF)

V(A) POR threshold, falling

2

2.2

2.4

V

V(AC_REG)

Regulated Forward V(A)–V(C)

Threshold

5.8

9.1

12.4

mV

V(AC_REV)

V(A)–V(C) Threshold for Fast Reverse

Current Blocking

–6.5

–5.5

–1.3

mV

V(AC_FWD)

V(A)–V(C) Threshold for Reverse to

Forward transition

150

177

220

mV

V(DGATE) – V(A)

Gate Drive Voltage

3 V < V(S) < 5 V

7

V

5 V < V(S) < 65 V

10

11.5

13

V

I(DGATE)

Peak Gate Source current

V(A) – V(C) = 100 mV, V(DGATE) – V(A) =

1 V

60

mA

Peak Gate Sink current

V(A) – V(C) = –12 mV, V(DGATE) – V(A) =

11 V

2670

mA

I(DGATE)

Regulation sink current

V(A) – V(C) = 0 V, V(DGATE) – V(A) = 11 V

8.4

14.9

µA

I(C)

Cathode leakage Current

V(A) = –14 V, V(C) = 12 V

4

9

32

µA

HIGH SIDE CONTROLLER (HGATE, OUT, SNS, SW, OV)

V(HGATE) – V(OUT)

Gate Drive Voltage

3 V < V(S) < 5 V

7

V

5 V < V(S) < 65 V

10

11.1

14.5

V

I(HGATE)

Source Current

39

55

75

µA

Sink Current

V(OV) > V(OVR)

168

260

mA

6.6 Switching Characteristics

TJ = –55°C to +125°C; typical values at TJ = 25°C, V(A) = V(C) = V(OUT) = V(VS) = 12V, V(AC) = 20 mV, C(VCAP) = 0.1 µF,

V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tDGATE_OFF(dly)

DGATE Turnoff Delay during reverse

voltage detection

V(A) – V(C) = +30 mV to –100 mV

to V(DGATE–A) < 1 V, C(DGATE–A) = 10

nF

0.5

0.875

µs

tDGATE_ON(dly)

DGATE Turnon Delay during forward

voltage detection

V(A) – V(C) = –20 mV to +700

mV to V(DGATE-A) > 5 V, C(DGATE-A) =

10 nF

0.8

1.6

µs

tEN(dly)_DGATE

DGATE Turnon Delay during EN/

UVLO

EN/UVLO ↑ to V(DGATE-A) > 5V,

C(DGATE-A) = 10 nF

98

175

270

µs

tEN_OFF(deg)_DGATE

DGATE Turnoff Deglitch during EN/

UVLO

EN/UVLO ↓ to DGATE ↓

8.1

µs

tEN_OFF(deg)_HGATE

HGATE Turnoff Deglitch during EN/

UVLO

EN/UVLO ↓ to HGATE ↓

3

4.6

6

µs

tOVP_OFF(deg)_HGAT

E

HGATE Turnoff Deglitch during OV

OV ↑ to HGATE ↓

3.98

5.4

µs

tOVP_ON(deg)_HGATE HGATE Turnon Deglitch during OV

OV ↓ to HGATE ↑

2.95

µs

LM7481

SNOSDD9 – DECEMBER 2022

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