LTC2855 datasheet(15/24 Pages) AD

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LTC2862A

Rev. A

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The LTC2862A uses fully symmetric positive and negative

receiver thresholds VTH– and VTH+ (typically ±125mV) to

maintaingooddutycyclesymmetryatlowsignallevels.The

failsafe operation is performed with a window comparator

to determine when the differential input voltage falls above

the VTFS failsafe threshold (typically –75mV) but below

the VTH+ threshold. If this condition persists for more

than about 40ns for the LTC2862A-1 or 1.2µs for the

LTC2862A-2 the failsafe condition is asserted and the RO

pin is forced to the logic 1 state. This circuit provides full

failsafe operation and a large dynamic signal hysteresis of

~250mV between VTH– and VTH+ with no negative impact

to receiver duty cycle symmetry, as shown in Figure 9.

The input signal in Figure 9 was obtained by driving a

10Mbps RS485 signal through 1000 feet of cable, thereby

attenuating it to a ±200mV signal with slow rise and fall

times.GooddutycyclesymmetryisobservedatROdespite

the degraded input signal.

The failsafe circuit has been enhanced with noise filtering

to exit the failsafe state. In the absence of noise filtering, a

noisetransientthatmomentarilyforcestheA-Bdifferential

voltage below the VTH– receiver threshold will cause the

RO output to go low, which may be interpreted as a false

start character by the microcontroller. The LTC2862A

receiver reduces these false signals by low pass filtering

the signal to exit the failsafe state. The noise filtering in the

failsafe circuit of the LTC2862A-2 is much greater than in

the LTC2862A-1, commensurate with its lower data rate.

For example, the LTC2862A-1 exits the failsafe state when

a –1V differential pulse of about 3ns duration is applied,

whiletheLTC2862A-2requiresa–1Vpulseofabout400ns

duration to exit the failsafe state. (The minimum pulse

widths to enter or exit the failsafe state are not tested in

production, but the underlying filtering is reflected in the

tFSN, tFSX, tFSNS, and tFSXS measurements).

Enhanced Receiver Noise Immunity

An additional benefit of the fully symmetric receiver

thresholds is enhanced receiver noise immunity. The

differential input signal must go above the positive

threshold to register as a logic 1 and go below the

negative threshold to register as a logic 0. This provides

a hysteresis of 250mV (typical) at the receiver inputs for

any valid data signal. (An invalid data condition such as

a DC sweep of the receiver inputs will produce a different

observed hysteresis due to the activation of the failsafe

circuit.) Competing devices that employ a negative offset

of the input threshold voltage generally have a much

smaller hysteresis and subsequently have lower receiver

noise immunity.

The LTC2862A-2 provides additional noise immunity

by adding low-pass filtering to the differential signal in

its receiver. Commensurate with its maximum data rate

of 250kbps, the LTC2862A-2 receiver attenuates high

frequency signals above approximately 660kHz. This low-

pass filter removes high frequency noise transients that

might otherwise be interpreted as data. (High frequency

noisefilteringisnottestedinproduction,buttheunderlying

filtering is reflected in the tPLHR, tPHLR, tPLHRS, and tPHLRS

measurements).

RS485 Network Biasing

RS485 networks are usually biased with a resistive divider

to generate a differential voltage of ≥200mV on the data

lines, which establishes a logic 1 state (the idle state)

when all the transmitters on the network are disabled. The

values of the biasing resistors are not fixed, but depend

on the number and type of transceivers on the line and

the number and value of terminating resistors. Therefore,

the values of the biasing resistors must be customized

to each specific network installation, and may change if

nodes are added to or removed from the network.

TheinternalfailsafefeatureoftheLTC2862Aeliminatesthe

need for external network biasing resistors provided they

are used in a network of transceivers with similar internal

failsafe features. The LTC2862A transceivers will operate

correctly on biased, unbiased, or under-biased networks.

Hi-Z State

The receiver output is internally driven high (to VCC) or

low (to GND) with no external pull-up needed. When the

receiver is disabled the RO pin becomes Hi-Z with a 250k

pull-up resistor to VCC.

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