LTC2855 datasheet(16/24 Pages) AD

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LTC2862A

Rev. A

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High Receiver Input Resistance

The bus receiver input load from A or B to GND is less than

one-seventh unit load, permitting a total of 224 receivers

per system without exceeding the RS485 receiver loading

specification.Theinputloadofthereceiverisunaffectedby

enabling/disablingthereceiverorbypowering/unpowering

the part.

Supply Current

The unloaded static supply currents in these devices

are low — typically 1.1mA for non slew limited devices

and 3.5mA for slew limited devices. In applications

with resistively terminated cables, the supply current is

dominatedbythedriverload.Forexample,whenusingtwo

120Ω terminators with a differential driver output voltage

of 2V, the DC load current is 33mA, which is sourced by

thepositivevoltagesupply.Powersupplycurrentincreases

with toggling data due to capacitive loading and this term

can increase significantly at high data rates. A plot of

the supply current vs data rate is shown in the Typical

Performance Characteristics of this data sheet.

During fault conditions with a positive voltage larger than

thesupplyvoltageappliedtothetransmitterpins,orduring

transmitter operation with a high positive common mode

voltage, positive current of up to 80mA may flow from the

transmitter pins back to VCC. If the system power supply

or loading cannot sink this excess current, a 5.6V 1W

1N4734 Zener diode may be placed between VCC and GND

to prevent an overvoltage condition on VCC.

The LTC2862A contains a supply undervoltage lockout

circuit that enables the transmitter and receiver outputs

when VCC exceeds ~2.7V and disables the transmitter and

receiver outputs when VCC falls below ~2.5V.

When the LTC2862A is unpowered, the logic inputs (DE,

DI, RE) are high impedance for voltages > 0V. Each input

has a diode clamp to GND that will conduct if a negative

voltage sufficient to forward bias the diode (~ –0.6V at

25°C)isappliedtothepad.TheROoutputcontainsaCMOS

driver with parasitic diodes to GND and VCC. The diode to

GND will conduct if forward biased by a negative voltage

below GND, while the diode to VCC will conduct if forward

biased by a positive voltage above VCC. If VCC is low, this

APPLICATIONS INFORMATION

will result in the RO line being clamped to approximately

0.6V above VCC. The impedance of the logic inputs and the

RO output are not tested with the LTC2862A unpowered.

Shutdown Mode Delay

The LTC2862A features a low power shutdown mode

that is entered when both the driver and the receiver

are simultaneously disabled (pin DE low and RE high).

A shutdown mode delay of approximately 250ns (not

tested in production) is imposed after this state is received

before the chip enters shutdown. If either DE goes high

or RE goes low during this delay, the delay timer is reset

and the chip does not enter shutdown. This reduces the

chance of accidentally entering shutdown if DE and RE are

driven in parallel by a slowly changing signal or if DE and

RE are driven by two independent signals with a timing

skew between them.

This shutdown mode delay does not affect the outputs of

the transmitter and receiver, which start to switch to the

high impedance state upon the reception of their respec-

tive disable signals as defined by the parameters tSHDND

and tSHDNR. The shutdown mode delay affects only the

time when all the internal circuits that draw DC power

from VCC are turned off.

High Speed Considerations

Agroundplanelayoutwitha0.1µFbypasscapacitorplaced

less than 7mm away from the VCC pin is recommended.

The PC board traces connected to signals A/B should be

symmetrical and as short as possible to maintain good

differential signal integrity. To minimize capacitive effects,

the differential signals should be separated by more than

the width of a trace and should not be routed on top of

each other if they are on different signal planes.

Care should be taken to route outputs away from any

sensitive inputs to reduce feedback effects that might

cause noise, jitter, or even oscillations.

The logic inputs have a typical hysteresis of 100mV to

provide noise immunity. Fast edges on the outputs can

cause glitches in the ground and power supplies which are

exacerbated by capacitive loading. If a logic input is held

near its threshold (typically VCC/2), a noise glitch from a

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