L99DZ100GP datasheet(51/197 Pages) STMICROELECTRONICS

51 / 197 page

DS11546 Rev 5

51/197

L99DZ100G, L99DZ100GP

Electrical specifications

196

3.4.21

Fail safe low-side switch

The voltages are referred to power ground and currents are assumed positive, when the

current flows into the pin. 6 V ≤ VS ≤ 18 V; Tj = 40 °C to 150 °C, unless otherwise specified.

IECDR

Current into ECDR

Vtarget(3) > VECV + 500 mV;

VECDR = 3.5 V

-100

-10

µA

Vtarget(3) < VECV - 500 mV;

VECDR = 1.0 V; Vtarget = 0 V;

VECV = 0.5 V

100

µA

Recdrdis

Pull-down resistance at

ECDR in fast discharge

mode and while EC-mode

is off

VECDR = 0.7 V; ECON = ‘1’,

EC<5:0> = 0 or ECON = ‘0’

kΩ

1. Bit ECV_HV (Config Reg) ='1' or ‘0’: ECV voltage, where IIECDR can change sign.

2. 1 LSB (Least Significant Bit) = 23.8 mV typ

3. Vtarget is set by bits EC<5:0> (CR 11) and bit ECV_HV (Config Reg); tested for each individual bit.

Table 26. Electro-chrome mirror driver (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Table 27. Fail safe low-side switch

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VOUT_max

Max output voltage in

case of missing supply

IOUT = 1 mA; VS = VSREG = 0 V

2.5

RDSON

DC output resistance

ILOAD = 250 mA; Tj = 25 °C

1.4

Ω

ILOAD = 250 mA; Tj = 130 °C

2.2

Ω

IOLimit

Overcurrent limitation

8 V < VS < 16 V

500

1500

tONHL

Turn on delay time to

10% VOUT

100

µs

tOFFLH

Turn off delay time to

90% VOUT

100

µs

tSCF

Short circuit filter time

µs

dVmax/dt

Maximum external

applied slew rate on

LS1_FSO and LS2_FSO

without switching on LS

Guaranteed by design

V/µs

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