L99DZ100GP datasheet(93/197 Pages) STMICROELECTRONICS

93 / 197 page

DS11546 Rev 5

93/197

L99DZ100G, L99DZ100GP

Application information

196

Dominant TxDC time out

If TXD_C is in dominant state (low) for t > tdom(TxDC) the transmitter will be disabled,

CAN_TXD_DOM (SR 2) will be latched and can be read and optionally cleared by SPI. The

transmitter remains disabled until the status register is cleared.

CAN Permanent Recessive

If TXD_C changes to dominant (low) state but CAN bus does not follow for 4 times, the

transmitter will be disabled, CAN_PERM_REC (SR 2) will be latched and can be read and

optionally cleared by SPI. The transmitter remains disabled until the status register is

cleared.

CAN Permanent Dominant

If the bus state is dominant (low) for t > tCAN a permanent dominant status will be detected.

CAN_PERM_DOM (SR 2) will be latched and can be read and optionally cleared by SPI.

The transmitter will not be disabled.

RXDC Permanent Recessive

If RXD_C pin is clamped to recessive (high) state, the controller is not able to recognize a

bus dominant state and could start messages at any time, which results in disturbing the

overall bus communication. Therefore, if RXD_C does not follow TXD_C for 4 times the

transmitter will be disabled. CAN_RXD_REC (SR 2) will be latched and can be read and

optionally cleared by SPI. The transmitter remains disabled until the status register is

cleared.

4.11

Serial Peripheral Interface (ST SPI Standard)

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition

of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin is needed to communicate with the device. A fault condition

can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag

(fault condition) of the device.



Chip Select Not (CSN)

The input Pin is used to select the serial interface of this device. When CSN is high, the

output Pin (DO) is in high impedance state. A low signal activates the output driver and

a serial communication can be started.

The state during CSN = 0 is called a communication frame.

If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not

block the signal line for other SPI nodes.



Serial Data In (DI)

The input Pin is used to transfer data serial into the device. The data applied to the DI is

sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift

transferred to Data Input Register. The writing to the selected Data Input Register is

only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN

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