L99DZ100GP datasheet(80/197 Pages) STMICROELECTRONICS

80 / 197 page

Application information

L99DZ100G, L99DZ100GP

80/197

DS11546 Rev 5

This actually produces an additional watchdog failure but the watchdog fail counter will

remain at maximum value of 15 failures.

This sequence is repeated until a valid watchdog trigger event is performed by writing

TRIG = 1.

In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit

WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device

enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe

low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for

more details.

The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are

split into 3 parts. First diagram shows the functional behavior of the watchdog without any

error. The second diagram covers the behavior covering all the error conditions, which can

affect the watchdog behavior. Figure 26: Watchdog in Flash mode shows the transition in

and out of Flash modes. Figure 24, Figure 25 and Figure 26 can be overlapped to get all the

possible state transitions under all circumstances. For a better readability, they were split in

normal operating, operating with errors and Flash mode.

Figure 24. Watchdog in normal operating mode (no errors)

L99DZ100GP Datasheet(PDF) 80 Page - STMicroelectronics