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AM85C30 Datasheet(PDF) 2 Page - Advanced Micro Devices

Part # AM85C30
Description  Enhanced Serial Communications Controller
PDF  68 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM85C30 Datasheet(HTML) 2 Page - Advanced Micro Devices

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AMD
2
Am85C30
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
s A 10
× 19 bit SDLC/HDLC frame status FIFO array
s A 14-bit SDLC/HDLC frame byte counter
s Automatic SDLC/HDLC opening frame flag
transmission
s TxD pin forced High in SDLC NRZI mode after
closing flag
s Automatic SDLC/HDLC Tx underrun/EOM flag
reset
s Automatic SDLC/HDLC Tx CRC generator reset/
preset
s
RTS synchronization to closing SDLC/HDLC flag
DTR/REQ deactivation delay significantly reduced
s External PCLK to
RxC or TxC synchronization
requirement eliminated for PCLK divide-by-four
operation
Other enhancements to improve the Am85C30 inter-
face capabilities include:
s Write data valid setup time to falling edge of
WR
requirement eliminated
s Reduced
INT response time
s Reduced access recovery time (tRC) to 3 PCLK
best case (3 1/2 PCLK worst case)
s Improved
Wait timing
s Write Registers WR3, WR4, WR5, and WR10
made readable
s Lower priority interrupt masking without
INTACK
s Complete SDLC/HDLC CRC character reception
BLOCK DIAGRAM
Data
Control
CPU
Bus VO
Internal
Control
Logic
Internal Bus
Channel
A
Registers
Interrupt
Control
Logic
Channel
B
Registers
+5 V GND PCLK
Channel A
Channel B
Control
Logic
Transmitter
Receiver
Baud
Rate
Generator
10
×19 Bit
Frame
Status
FIFO
Interrupt
Control Lines
5
10216F-1
8
TxDA
RxDA
RTxCA
TRxCA
DTR/REQA
SYNCA
W/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
RTxCB
TRxCB
DTR/REQB
SYNCB
W/REQB
RTSB
CTSB
DCDB
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