AM85C30 datasheet(23/68 Pages) AMD

23 / 68 page

AMD

Am85C30

Write Register 12

D7 D6 D5 D4 D3 D2 D1 D0

TC0

TC1

TC2

TC3

TC4

TC5

TC6

TC7

Lower Byte of

Time Constant

Write Register 14

D7 D6 D5 D4 D3 D2 D1 D0

BR Generator Enable

BR Generator Source

DTR/Request Function

Auto Echo

Local Loopback

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

6-Bit/

8-Bit Sync

Loop Mode

Abort/

Flag on Underrun

Mark/

Flag Idle

Go Active on Roll

NRZ

NRZI

FM1 (Transition = 1)

FM0 (Transition = 0)

CRC Preset ‘1’ or ‘0’

Write Register 13

D7 D6 D5 D4 D3 D2 D1 D0

TC8

TC9

TC10

TC11

TC12

TC13

TC14

TC15

Upper Byte of

Time Constant

Null Command

Enter Search Mode

Reset Missing Clock

Disable DPLL

Set Source = BR Generator

Set Source =

RTxC

Set FM Mode

Set NRZI Mode

Write Register 15

D7 D6 D5 D4 D3 D2 D1 D0

SDLC/HDLC Enhancements Enable*

Zero Count IE

× 19 Bit FIFO Enable*

DCD IE

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

Break/Abort IE

* Added Enhancement

Figure 9. Write Register Bit Functions (continued)

10216F-13

(concluded)

Am85C30 Timing

The ESCC generates internal control signals from

and

RD that are related to PCLK. Since PCLK has no

phase relationship with

WR and RD, the circuitry gener-

ating these internal control signals must provide time for

metastable conditions to disappear. This gives rise to a

recovery time related to PCLK. The recovery time ap-

plies only between bus transactions involving the

ESCC. The recovery time required for proper operation

is specified from the falling edge of

WR or RD in the first

transaction involving the ESCC, to the falling edge of

WR or RD in the second transaction involving the

ESCC. This time must be at least 3 1/2 PCLK regardless

of which register or channel is being accessed.

Read Cycle Timing

Figure 10 illustrates Read cycle timing. Addresses on

B and D/C and the status on INTACK must remain sta-

ble throughout the cycle. If

CE falls after RD falls or if it

rises before

RD rises, the effective RD is shortened.

Write Cycle Timing

Figure 11 illustrates Write cycle timing. Addresses on

B and D/C and the status on INTACK must remain

stable throughout the cycle. If

CE falls after WR falls or if

it rises before

WR rises, the effective WR is shortened.

Data must be valid before the rising edge of

WR.

AM85C30 Datasheet(PDF) 23 Page - Advanced Micro Devices

AM85C30 Datasheet(HTML) 23 Page - Advanced Micro Devices

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